library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity D_FF is
   port(
      Q : out signed(15 downto 0);      --output connected to the adder
      Clk :in std_logic;      -- Clock input
      D :in  signed(15 downto 0)      -- Data input from the MCM block.
   );
end D_FF;

architecture D_FF_arch of D_FF is

--signal qt : signed(15 downto 0) := (others => '0');

begin

--Q <= qt;

process(Clk)
begin
  if ( rising_edge(Clk) ) then
    Q <= D;
  end if;      
end process;

end D_FF_arch;

