

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity FIR_filter is
port(   Clk : in std_logic; --clock signal
        Xin : in signed(7 downto 0); --input signal
        Yout : out signed(15 downto 0)  --filter output
        );
end FIR_filter;

architecture FIR_filter_arch of FIR_filter is

component D_FF is
   port(
      Q : out signed(15 downto 0);      --output connected to the adder
      Clk :in std_logic;      -- Clock input
      D :in  signed(15 downto 0)      -- Data input from the MCM block.
   );
end component; 

 
   
signal a0,a1,a2 : signed(7 downto 0) := (others => '0');
signal Mult_Coeff0,Mult_Coeff1,Mult_Coeff2,add_out0,add_out1 : signed(15 downto 0) := (others => '0');
signal Q1,Q2 : signed(15 downto 0) := (others => '0');

begin

--filter coefficient initializations.
--a = [-2 -1 3].
a0 <= to_signed(-2,8);
a1 <= to_signed(-1,8);
a2 <= to_signed(3,8);


--Multiple constant multiplications.
Mult_Coeff2 <= a2*Xin;
Mult_Coeff1 <= a1*Xin;
Mult_Coeff0 <= a0*Xin;

--adders
add_out0 <= Q1 + Mult_Coeff1;
add_out1 <= Q2 + Mult_Coeff0;


--flipflops(for introducing a delay).
dff1 : D_FF port map(Q1,Clk,Mult_Coeff2);
dff2 : D_FF port map(Q2,Clk,add_out0);


--an output produced at every positive edge of clock cycle.
process(Clk)
begin
    if(rising_edge(Clk)) then
        Yout <= add_out1;
    end if;
end process;
   
end FIR_filter_arch;



