University of LiègeULgFaculty of EngineeringFacSALibrary News   
Seminar : Transistor scaling and related metrology challenges


History of micro-electronic is intimately linked to history of transistor scaling. Since the first micro-processor in 1971, the amount of transistors per chip has been multiplied by ten millions (sometimes reaching more than twenty billions of transistors) while their gate size was divided by one thousand. This lecture will first review the major evolutions that brought us to the current sub-30nm transistor generation.

Further scaling towards sub-10nm technology nodes (N7, N5,…) is involving intensive research on the introduction of new materials (Ge, III-V, graphene,…) and device architectures (FinFETs, GAA-FETs, thin-film FETs,.). The more complex underlying physics and the exponential increase of technological options is leading to growing integration challenges, and hence to growing need for advanced metrology solutions to understand the complex mechanisms involved and to allow a prospective work. In the second part of this lecture, metrology solutions will be presented with a special focus on 2D/3D dopant and/or carrier profiling techniques with nanometer resolution.